CUDA

CUDA

CUDA

Parallel computing platform and programming model


Compute Unified Device Architecture (CUDA) is a parallel computing platform and application programming interface (API) that allows software to use certain types of graphics processing units (GPUs) for accelerated general-purpose processing, an approach called general-purpose computing on GPUs (GPGPU). CUDA API and its runtime: The CUDA API is an extension of the C programming language that adds the ability to specify thread-level parallelism in C and also to specify GPU device specific operations (like moving data between the CPU and the GPU). [1] CUDA is a software layer that gives direct access to the GPU's virtual instruction set and parallel computational elements for the execution of compute kernels.[2] In addition to drivers and runtime kernels, the CUDA platform includes compilers, libraries and developer tools to help programmers accelerate their applications.

Quick Facts Developer(s), Initial release ...

CUDA is designed to work with programming languages such as C, C++, Fortran and Python. This accessibility makes it easier for specialists in parallel programming to use GPU resources, in contrast to prior APIs like Direct3D and OpenGL, which required advanced skills in graphics programming.[3] CUDA-powered GPUs also support programming frameworks such as OpenMP, OpenACC and OpenCL.[4][2]

CUDA was created by Nvidia in 2006.[5] When it was first introduced, the name was an acronym for Compute Unified Device Architecture,[6] but Nvidia later dropped the common use of the acronym and no longer uses it.[when?]

Background

The graphics processing unit (GPU), as a specialized computer processor, addresses the demands of real-time high-resolution 3D graphics compute-intensive tasks. By 2012, GPUs had evolved into highly parallel multi-core systems allowing efficient manipulation of large blocks of data. This design is more effective than general-purpose central processing unit (CPUs) for algorithms in situations where processing large blocks of data is done in parallel, such as:

Ian Buck, while at Stanford in 2000, created an 8K gaming rig using 32 GeForce cards, then obtained a DARPA grant to perform general purpose parallel programming on GPUs. He then joined Nvidia, where since 2004 he has been overseeing CUDA development. In pushing for CUDA, Jensen Huang aimed for the Nvidia GPUs to become a general hardware for scientific computing. CUDA was released in 2006. Around 2015, the focus of CUDA changed to neural networks.[7]

Ontology

The following table offers a non-exact description for the ontology of CUDA framework.

More information memory (hardware), memory (code, or variable scoping) ...

Programming abilities

Example of CUDA processing flow
  1. Copy data from main memory to GPU memory
  2. CPU initiates the GPU compute kernel
  3. GPU's CUDA cores execute the kernel in parallel
  4. Copy the resulting data from GPU memory to main memory

The CUDA platform is accessible to software developers through CUDA-accelerated libraries, compiler directives such as OpenACC, and extensions to industry-standard programming languages including C, C++, Fortran and Python. C/C++ programmers can use 'CUDA C/C++', compiled to PTX with nvcc, Nvidia's LLVM-based C/C++ compiler, or by clang itself.[8] Fortran programmers can use 'CUDA Fortran', compiled with the PGI CUDA Fortran compiler from The Portland Group.[needs update] Python programmers can use the cuNumeric library to accelerate applications on Nvidia GPUs.

In addition to libraries, compiler directives, CUDA C/C++ and CUDA Fortran, the CUDA platform supports other computational interfaces, including the Khronos Group's OpenCL,[9] Microsoft's DirectCompute, OpenGL Compute Shader and C++ AMP.[10] Third party wrappers are also available for Python, Perl, Fortran, Java, Ruby, Lua, Common Lisp, Haskell, R, MATLAB, IDL, Julia, and native support in Mathematica.

In the computer game industry, GPUs are used for graphics rendering, and for game physics calculations (physical effects such as debris, smoke, fire, fluids); examples include PhysX and Bullet. CUDA has also been used to accelerate non-graphical applications in computational biology, cryptography and other fields by an order of magnitude or more.[11][12][13][14][15]

CUDA provides both a low level API (CUDA Driver API, non single-source) and a higher level API (CUDA Runtime API, single-source). The initial CUDA SDK was made public on 15 February 2007, for Microsoft Windows and Linux. Mac OS X support was later added in version 2.0,[16] which supersedes the beta released February 14, 2008.[17] CUDA works with all Nvidia GPUs from the G8x series onwards, including GeForce, Quadro and the Tesla line. CUDA is compatible with most standard operating systems.

CUDA 8.0 comes with the following libraries (for compilation & runtime, in alphabetical order):

  • cuBLAS – CUDA Basic Linear Algebra Subroutines library
  • CUDART – CUDA Runtime library
  • cuFFT – CUDA Fast Fourier Transform library
  • cuRAND – CUDA Random Number Generation library
  • cuSOLVER – CUDA based collection of dense and sparse direct solvers
  • cuSPARSE – CUDA Sparse Matrix library
  • NPP – NVIDIA Performance Primitives library
  • nvGRAPH – NVIDIA Graph Analytics library
  • NVML – NVIDIA Management Library
  • NVRTC – NVIDIA Runtime Compilation library for CUDA C++

CUDA 8.0 comes with these other software components:

  • nView – NVIDIA nView Desktop Management Software
  • NVWMI – NVIDIA Enterprise Management Toolkit
  • GameWorks PhysX – is a multi-platform game physics engine

CUDA 9.0–9.2 comes with these other components:

  • CUTLASS 1.0 – custom linear algebra algorithms,
  • NVIDIA Video Decoder was deprecated in CUDA 9.2; it is now available in NVIDIA Video Codec SDK

CUDA 10 comes with these other components:

  • nvJPEG – Hybrid (CPU and GPU) JPEG processing

CUDA 11.0–11.8 comes with these other components:[18][19][20][21]

  • CUB is new one of more supported C++ libraries
  • MIG multi instance GPU support
  • nvJPEG2000 – JPEG 2000 encoder and decoder

Advantages

CUDA has several advantages over traditional general-purpose computation on GPUs (GPGPU) using graphics APIs:

  • Scattered reads  code can read from arbitrary addresses in memory.
  • Unified virtual memory (CUDA 4.0 and above)
  • Unified memory (CUDA 6.0 and above)
  • Shared memory  CUDA exposes a fast shared memory region that can be shared among threads. This can be used as a user-managed cache, enabling higher bandwidth than is possible using texture lookups.[22]
  • Faster downloads and readbacks to and from the GPU
  • Full support for integer and bitwise operations, including integer texture lookups

Limitations

  • Whether for the host computer or the GPU device, all CUDA source code is now processed according to C++ syntax rules.[23] This was not always the case. Earlier versions of CUDA were based on C syntax rules.[24] As with the more general case of compiling C code with a C++ compiler, it is therefore possible that old C-style CUDA source code will either fail to compile or will not behave as originally intended.
  • Interoperability with rendering languages such as OpenGL is one-way, with OpenGL having access to registered CUDA memory but CUDA not having access to OpenGL memory.
  • Copying between host and device memory may incur a performance hit due to system bus bandwidth and latency (this can be partly alleviated with asynchronous memory transfers, handled by the GPU's DMA engine).
  • Threads should be running in groups of at least 32 for best performance, with total number of threads numbering in the thousands. Branches in the program code do not affect performance significantly, provided that each of 32 threads takes the same execution path; the SIMD execution model becomes a significant limitation for any inherently divergent task (e.g. traversing a space partitioning data structure during ray tracing).
  • No emulation or fallback functionality is available for modern revisions.
  • Valid C++ may sometimes be flagged and prevent compilation due to the way the compiler approaches optimization for target GPU device limitations.[citation needed]
  • C++ run-time type information (RTTI) and C++-style exception handling are only supported in host code, not in device code.
  • In single-precision on first generation CUDA compute capability 1.x devices, denormal numbers are unsupported and are instead flushed to zero, and the precision of both the division and square root operations are slightly lower than IEEE 754-compliant single precision math. Devices that support compute capability 2.0 and above support denormal numbers, and the division and square root operations are IEEE 754 compliant by default. However, users can obtain the prior faster gaming-grade math of compute capability 1.x devices if desired by setting compiler flags to disable accurate divisions and accurate square roots, and enable flushing denormal numbers to zero.[25]
  • Unlike OpenCL, CUDA-enabled GPUs are only available from Nvidia.[26] Attempts to implement CUDA on other GPUs include:
    • Project Coriander: Converts CUDA C++11 source to OpenCL 1.2 C. A fork of CUDA-on-CL intended to run TensorFlow.[27][28][29]
    • CU2CL: Convert CUDA 3.2 C++ to OpenCL C.[30]
    • GPUOpen HIP: A thin abstraction layer on top of CUDA and ROCm intended for AMD and Nvidia GPUs. Has a conversion tool for importing CUDA C++ source. Supports CUDA 4.0 plus C++11 and float16.
    • ZLUDA is a drop-in replacement for CUDA on AMD GPUs and formerly Intel GPUs with near-native performance.[31] The developer, Andrzej Janik, was separately contracted by both Intel and AMD to develop the software in 2021 and 2022, respectively. However, neither company decided to release it officially due to the lack of a business use case. AMD's contract included a clause that allowed Janik to release his code for AMD independently, allowing him to release the new version that only supports AMD GPUs.[32]
    • chipStar can compile and run CUDA/HIP programs on advanced OpenCL 3.0 or Level Zero platforms.[33]

Example

This example code in C++ loads a texture from an image into an array on the GPU:

texture<float, 2, cudaReadModeElementType> tex;

void foo()
{
  cudaArray* cu_array;

  // Allocate array
  cudaChannelFormatDesc description = cudaCreateChannelDesc<float>();
  cudaMallocArray(&cu_array, &description, width, height);

  // Copy image data to array
  cudaMemcpyToArray(cu_array, image, width*height*sizeof(float), cudaMemcpyHostToDevice);

  // Set texture parameters (default)
  tex.addressMode[0] = cudaAddressModeClamp;
  tex.addressMode[1] = cudaAddressModeClamp;
  tex.filterMode = cudaFilterModePoint;
  tex.normalized = false; // do not normalize coordinates

  // Bind the array to the texture
  cudaBindTextureToArray(tex, cu_array);

  // Run kernel
  dim3 blockDim(16, 16, 1);
  dim3 gridDim((width + blockDim.x - 1)/ blockDim.x, (height + blockDim.y - 1) / blockDim.y, 1);
  kernel<<< gridDim, blockDim, 0 >>>(d_data, height, width);

  // Unbind the array from the texture
  cudaUnbindTexture(tex);
} //end foo()

__global__ void kernel(float* odata, int height, int width)
{
   unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
   unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
   if (x < width && y < height) {
      float c = tex2D(tex, x, y);
      odata[y*width+x] = c;
   }
}

Below is an example given in Python that computes the product of two arrays on the GPU. The unofficial Python language bindings can be obtained from PyCUDA.[34]

import pycuda.compiler as comp
import pycuda.driver as drv
import numpy
import pycuda.autoinit

mod = comp.SourceModule(
    """
__global__ void multiply_them(float *dest, float *a, float *b)
{
  const int i = threadIdx.x;
  dest[i] = a[i] * b[i];
}
"""
)

multiply_them = mod.get_function("multiply_them")

a = numpy.random.randn(400).astype(numpy.float32)
b = numpy.random.randn(400).astype(numpy.float32)

dest = numpy.zeros_like(a)
multiply_them(drv.Out(dest), drv.In(a), drv.In(b), block=(400, 1, 1))

print(dest - a * b)

Additional Python bindings to simplify matrix multiplication operations can be found in the program pycublas.[35]

 
import numpy
from pycublas import CUBLASMatrix

A = CUBLASMatrix(numpy.mat([[1, 2, 3], [4, 5, 6]], numpy.float32))
B = CUBLASMatrix(numpy.mat([[2, 3], [4, 5], [6, 7]], numpy.float32))
C = A * B
print(C.np_mat())

while CuPy directly replaces NumPy:[36]

import cupy

a = cupy.random.randn(400)
b = cupy.random.randn(400)

dest = cupy.zeros_like(a)

print(dest - a * b)

GPUs supported

Supported CUDA Compute Capability versions for CUDA SDK version and Microarchitecture (by code name):

More information CUDA SDK Version(s), Tesla ...

Note: CUDA SDK 10.2 is the last official release for macOS, as support will not be available for macOS in newer releases.

CUDA Compute Capability by version with associated GPU semiconductors and GPU card models (separated by their various application areas):

More information Computecapability (version), Micro-architecture ...

'*' – OEM-only products

Version features and specifications

More information Feature support (unlisted features are supported for all compute capabilities), Compute capability (version) ...

[56]

Data types

More information Data type, Operation ...

Note: Any missing lines or empty entries do reflect some lack of information on that exact item.[57]


Tensor cores

More information FMA per cycle per tensor core, Supported since ...

Note: Any missing lines or empty entries do reflect some lack of information on that exact item.[60][61]

More information Tensor Core Composition, 7.0 ...

[69][70][71][72]

More information FP64 Tensor Core Composition, 8.0 ...

Technical Specification

More information Technical specifications, Compute capability (version) ...

Multiprocessor Architecture

More information Architecture specifications, Compute capability (version) ...

For more information read the Nvidia CUDA programming guide.[114]

Current and future usages of CUDA architecture

Comparison with competitors

CUDA competes with other GPU computing stacks: Intel OneAPI and AMD ROCm.

Where as Nvidia's CUDA is closed-source, Intel's OneAPI (and AMD ROCm) are open source.

Intel OneAPI

oneAPI is open source, and all the corresponding libraries are published on its GitHub Page.

Originally made by Intel, other hardware adopters are example Fujitsu and Huawei.

Unified Acceleration Foundation (UXL)

Unified Acceleration Foundation (UXL) is a new technology consortium that are working on the continuation of the OneAPI initiative, with to goal to create a new open standard accelerator software ecosystem, related open standards and specification projects through Working Groups and Special Interest Groups (SIGs). The goal will compete with Nvidia's CUDA. The main companies behind it are Intel, Google, ARM, Qualcomm, Samsung, Imagination, and VMware.[117]

AMD ROCm

ROCm[118] is an open source software stack for graphics processing unit (GPU) programming from Advanced Micro Devices (AMD).

See also


References

  1. Nvidia. "What is CUDA?". Nvidia. Retrieved 21 March 2024.
  2. Abi-Chahla, Fedy (June 18, 2008). "Nvidia's CUDA: The End of the CPU?". Tom's Hardware. Retrieved May 17, 2015.
  3. Zunitch, Peter (2018-01-24). "CUDA vs. OpenCL vs. OpenGL". Videomaker. Retrieved 2018-09-16.
  4. "OpenCL". NVIDIA Developer. 2013-04-24. Retrieved 2019-11-04.
  5. Shimpi, Anand Lal; Wilson, Derek (November 8, 2006). "Nvidia's GeForce 8800 (G80): GPUs Re-architected for DirectX 10". AnandTech. Retrieved May 16, 2015.
  6. Witt, Stephen (2023-11-27). "How Jensen Huang's Nvidia Is Powering the A.I. Revolution". The New Yorker. ISSN 0028-792X. Retrieved 2023-12-10.
  7. Vasiliadis, Giorgos; Antonatos, Spiros; Polychronakis, Michalis; Markatos, Evangelos P.; Ioannidis, Sotiris (September 2008). "Gnort: High Performance Network Intrusion Detection Using Graphics Processors" (PDF). Recent Advances in Intrusion Detection. Lecture Notes in Computer Science. Vol. 5230. pp. 116–134. doi:10.1007/978-3-540-87403-4_7. ISBN 978-3-540-87402-7.
  8. Schatz, Michael C.; Trapnell, Cole; Delcher, Arthur L.; Varshney, Amitabh (2007). "High-throughput sequence alignment using Graphics Processing Units". BMC Bioinformatics. 8: 474. doi:10.1186/1471-2105-8-474. PMC 2222658. PMID 18070356.
  9. "Use your Nvidia GPU for scientific computing". BOINC. 2008-12-18. Archived from the original on 2008-12-28. Retrieved 2017-08-08.
  10. "CUDA 1.1 – Now on Mac OS X". February 14, 2008. Archived from the original on November 22, 2008.
  11. Silberstein, Mark; Schuster, Assaf; Geiger, Dan; Patney, Anjul; Owens, John D. (2008). "Efficient computation of sum-products on GPUs through software-managed cache" (PDF). Proceedings of the 22nd annual international conference on Supercomputing – ICS '08 (PDF). Proceedings of the 22nd annual international conference on Supercomputing – ICS '08. pp. 309–318. doi:10.1145/1375527.1375572. ISBN 978-1-60558-158-3.
  12. "CUDA C Programming Guide v8.0" (PDF). nVidia Developer Zone. January 2017. p. 19. Retrieved 22 March 2017.
  13. Whitehead, Nathan; Fit-Florea, Alex. "Precision & Performance: Floating Point and IEEE 754 Compliance for Nvidia GPUs" (PDF). Nvidia. Retrieved November 18, 2014.
  14. "CUDA-Enabled Products". CUDA Zone. Nvidia Corporation. Retrieved 2008-11-03.
  15. Perkins, Hugh (2017). "cuda-on-cl" (PDF). IWOCL. Retrieved August 8, 2017.
  16. "CU2CL Documentation". chrec.cs.vt.edu.
  17. "pycublas". Archived from the original on 2009-04-20. Retrieved 2017-08-08.
  18. "CuPy". Retrieved 2020-01-08.
  19. "NVIDIA Quadro NVS 420 Specs". TechPowerUp GPU Database. 25 August 2023.
  20. Nvidia Xavier Specs on TechPowerUp (preliminary)
  21. Fused-Multiply-Add, actually executed, Dense Matrix
  22. as SASS since 7.5, as PTX since 8.0
  23. "Technical brief. NVIDIA Jetson AGX Orin Series" (PDF). nvidia.com. Retrieved 5 September 2023.
  24. "NVIDIA Ampere GA102 GPU Architecture" (PDF). nvidia.com. Retrieved 5 September 2023.
  25. In the Whitepapers the Tensor Core cube diagrams represent the Dot Product Unit Width into the height (4 FP16 for Volta and Turing, 8 FP16 for A100, 4 FP16 for GA102, 16 FP16 for GH100). The other two dimensions represent the number of Dot Product Units (4x4 = 16 for Volta and Turing, 8x4 = 32 for Ampere and Hopper). The resulting gray blocks are the FP16 FMA operations per cycle. Pascal without Tensor core is only shown for speed comparison as is Volta V100 with non-FP16 datatypes.
  26. "NVIDIA Turing Architecture Whitepaper" (PDF). nvidia.com. Retrieved 5 September 2023.
  27. "NVIDIA Tensor Core GPU" (PDF). nvidia.com. Retrieved 5 September 2023.
  28. shape x converted operand size, e.g. 2 tensor cores x 4x4x4xFP16/cycle = 256 Bytes/cycle
  29. = product first 3 table rows
  30. = product of previous 2 table rows; shape: e.g. 8x8x4xFP16 = 512 Bytes
  31. Sun, Wei; Li, Ang; Geng, Tong; Stuijk, Sander; Corporaal, Henk (2023). "Dissecting Tensor Cores via Microbenchmarks: Latency, Throughput and Numeric Behaviors". IEEE Transactions on Parallel and Distributed Systems. 34 (1): 246–261. arXiv:2206.02874. doi:10.1109/tpds.2022.3217824. S2CID 249431357.
  32. Raihan, Md Aamir; Goli, Negar; Aamodt, Tor (2018). "Modeling Deep Learning Accelerator Enabled GPUs". arXiv:1811.08309 [cs.MS].
  33. shape x converted operand size, e.g. 2 tensor cores x 4x4x4xFP16/cycle = 256 Bytes/cycle
  34. = product first 3 table rows
  35. = product of previous 2 table rows; shape: e.g. 8x8x4xFP16 = 512 Bytes
  36. Jia, Zhe; Maggioni, Marco; Smith, Jeffrey; Daniele Paolo Scarpazza (2019). "Dissecting the NVidia Turing T4 GPU via Microbenchmarking". arXiv:1903.07486 [cs.DC].
  37. Burgess, John (2019). "RTX ON – The NVIDIA TURING GPU". 2019 IEEE Hot Chips 31 Symposium (HCS). pp. 1–27. doi:10.1109/HOTCHIPS.2019.8875651. ISBN 978-1-7281-2089-8. S2CID 204822166.
  38. Jia, Zhe; Maggioni, Marco; Smith, Jeffrey; Daniele Paolo Scarpazza (2019). "Dissecting the NVidia Turing T4 GPU via Microbenchmarking". arXiv:1903.07486 [cs.DC].
  39. Burgess, John (2019). "RTX ON – The NVIDIA TURING GPU". 2019 IEEE Hot Chips 31 Symposium (HCS). pp. 1–27. doi:10.1109/HOTCHIPS.2019.8875651. ISBN 978-1-7281-2089-8. S2CID 204822166.
  40. dependent on device
  41. "Tegra X1". 9 January 2015.
  42. can only execute 160 integer instructions according to programming guide
  43. 128 according to . 64 from FP32 + 64 separate units?
  44. 64 by FP32 cores and 64 by flexible FP32/INT cores.
  45. 32 FP32 lanes combine to 16 FP64 lanes. Maybe lower depending on model.
  46. only supported by 16 FP32 lanes, they combine to 4 FP64 lanes
  47. depending on model
  48. Effective speed, probably over FP32 ports. No description of actual FP64 cores.
  49. Can also be used for integer additions and comparisons
  50. 2 clock cycles/instruction for each SM partition Burgess, John (2019). "RTX ON – The NVIDIA TURING GPU". 2019 IEEE Hot Chips 31 Symposium (HCS). pp. 1–27. doi:10.1109/HOTCHIPS.2019.8875651. ISBN 978-1-7281-2089-8. S2CID 204822166.
  51. Durant, Luke; Giroux, Olivier; Harris, Mark; Stam, Nick (May 10, 2017). "Inside Volta: The World's Most Advanced Data Center GPU". Nvidia developer blog.
  52. The schedulers and dispatchers have dedicated execution units unlike with Fermi and Kepler.
  53. Dispatching can overlap concurrently, if it takes more than one cycle (when there are less execution units than 32/SM Partition)
  54. Can dual issue MAD pipe and SFU pipe
  55. No more than one scheduler can issue 2 instructions at once. The first scheduler is in charge of warps with odd IDs. The second scheduler is in charge of warps with even IDs.
  56. shared memory only, no data cache
  57. shared memory separate, but L1 includes texture cache
  58. "H.6.1. Architecture". docs.nvidia.com. Retrieved 2019-05-13.
  59. Jia, Zhe; Maggioni, Marco; Staiger, Benjamin; Scarpazza, Daniele P. (2018). "Dissecting the NVIDIA Volta GPU Architecture via Microbenchmarking". arXiv:1804.06826 [cs.DC].
  60. "Tegra X1". 9 January 2015.
  61. Jia, Zhe; Maggioni, Marco; Smith, Jeffrey; Daniele Paolo Scarpazza (2019). "Dissecting the NVidia Turing T4 GPU via Microbenchmarking". arXiv:1903.07486 [cs.DC].
  62. Note that Jia, Zhe; Maggioni, Marco; Smith, Jeffrey; Daniele Paolo Scarpazza (2019). "Dissecting the NVidia Turing T4 GPU via Microbenchmarking". arXiv:1903.07486 [cs.DC]. disagrees and states 2 KiB L0 instruction cache per SM partition and 16 KiB L1 instruction cache per SM
  63. Jia, Zhe; Maggioni, Marco; Staiger, Benjamin; Scarpazza, Daniele P. (2018). "Dissecting the NVIDIA Volta GPU Architecture via Microbenchmarking". arXiv:1804.06826 [cs.DC].
  64. for access with texture engine only
  65. 25% disabled on RTX 4090
  66. "I.7. Compute Capability 8.x". docs.nvidia.com. Retrieved 2022-10-12.
  67. "Appendix F. Features and Technical Specifications" (PDF). (3.2 MiB), page 148 of 175 (Version 5.0 October 2012).
  68. "nVidia CUDA Bioinformatics: BarraCUDA". BioCentric. 2019-07-19. Retrieved 2019-10-15.
  69. "Part V: Physics Simulation". NVIDIA Developer. Retrieved 2020-09-11.

Further reading


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