Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) is a type of synchronous dynamic random-access memory with a high bandwidth ("double data rate") interface.

Released to the market in 2014,^[2][3][4] it is a variant of dynamic random-access memory (DRAM), of which some have been in use since the early 1970s,^[5] and a higher-speed successor to the DDR2 and DDR3 technologies.

DDR4 is not compatible with any earlier type of random-access memory (RAM) due to different signaling voltage and physical interface, besides other factors.

DDR4 SDRAM was released to the public market in Q2 2014, focusing on ECC memory,^[6] while the non-ECC DDR4 modules became available in Q3 2014, accompanying the launch of Haswell-E processors that require DDR4 memory.^[7]

The primary advantages of DDR4 over its predecessor, DDR3, include higher module density and lower voltage requirements, coupled with higher data rate transfer speeds. The DDR4 standard allows for DIMMs of up to 64 GB in capacity, compared to DDR3's maximum of 16 GB per DIMM.^{[1][8][failed verification]}

Unlike previous generations of DDR memory, prefetch has not been increased above the 8n used in DDR3;^[9]: 16 the basic burst size is eight 64-bit words, and higher bandwidths are achieved by sending more read/write commands per second. To allow this, the standard divides the DRAM banks into two or four selectable bank groups,^[10] where transfers to different bank groups may be done more rapidly.

Because power consumption increases with speed, the reduced voltage allows higher speed operation without unreasonable power and cooling requirements.

DDR4 operates at a voltage of 1.2 V with a frequency between 800 and 1600 MHz (DDR4-1600 through DDR4-3200), compared to frequencies between 400 and 1067 MHz (DDR3-800 through DDR3-2133)^{[11][lower-alpha 1]} and voltage requirements of 1.5 V of DDR3. Due to the nature of DDR, speeds are typically advertised as doubles of these numbers (DDR3-1600 and DDR4-2400 are common, while DDR4-3200, DDR4-4800 and DDR4-5000 are available but at a higher cost). Unlike DDR3's 1.35 V low voltage standard DDR3L, there is no DDR4L low voltage version of DDR4.^[13][14]

• 2005: Standards body JEDEC began working on a successor to DDR3 around 2005,^[16] about 2 years before the launch of DDR3 in 2007.^[17][18] The high-level architecture of DDR4 was planned for completion in 2008.^[19]
• 2007: Some advance information was published in 2007,^[20] and a guest speaker from Qimonda provided further public details in a presentation at the August 2008 San Francisco Intel Developer Forum (IDF).^{[20][21][22][23]} DDR4 was described as involving a 30 nm process at 1.2 volts, with bus frequencies of 2133 MT/s "regular" speed and 3200 MT/s "enthusiast" speed, and reaching market in 2012, before transitioning to 1 volt in 2013.^[21][23]
• 2009: In February, Samsung validated 40 nm DRAM chips, considered a "significant step" towards DDR4 development^[24] since in 2009, DRAM chips were only beginning to migrate to a 50 nm process.^[25]
• 2010: Subsequently, further details were revealed at MemCon 2010, Tokyo (a computer memory industry event), at which a presentation by a JEDEC director titled "Time to rethink DDR4"^[26] with a slide titled "New roadmap: More realistic roadmap is 2015" led some websites to report that the introduction of DDR4 was probably^[27] or definitely^[28][29] delayed until 2015. However, DDR4 test samples were announced in line with the original schedule in early 2011 at which time manufacturers began to advise that large scale commercial production and release to market was scheduled for 2012.^[2]
• 2011: In January, Samsung announced the completion and release for testing of a 2 GB^[1] DDR4 DRAM module based on a process between 30 and 39 nm.^[30] It has a maximum data transfer rate of 2133 MT/s at 1.2 V, uses pseudo open drain technology (adapted from graphics DDR memory^[31]) and draws 40% less power than an equivalent DDR3 module.^[30][32]
  In April, Hynix announced the production of 2 GB^[1] DDR4 modules at 2400 MT/s, also running at 1.2 V on a process between 30 and 39 nm (exact process unspecified),^[2] adding that it anticipated commencing high volume production in the second half of 2012.^[2] Semiconductor processes for DDR4 are expected to transition to sub-30 nm at some point between late 2012 and 2014.^{[33][34][needs update]}
• 2012: In May, Micron announced^[3] it is aiming at starting production in late 2012 of 30 nm modules.
  In July, Samsung announced that it would begin sampling the industry's first 16 GB^[1] registered dual inline memory modules (RDIMMs) using DDR4 SDRAM for enterprise server systems.^[35][36]
  In September, JEDEC released the final specification of DDR4.^[37]
• 2013: DDR4 was expected to represent 5% of the DRAM market in 2013,^[2] and to reach mass market adoption and 50% market penetration around 2015;^[2] as of 2013, however, adoption of DDR4 had been delayed and it was no longer expected to reach a majority of the market until 2016 or later.^[38] The transition from DDR3 to DDR4 is thus taking longer than the approximately five years taken for DDR3 to achieve mass market transition over DDR2.^[33] In part, this is because changes required to other components would affect all other parts of computer systems, which would need to be updated to work with DDR4.^[39]
• 2014: In April, Hynix announced that it had developed the world's first highest-density 128 GB module based on 8 Gbit DDR4 using 20 nm technology. The module works at 2133 MHz, with a 64-bit I/O, and processes up to 17 GB of data per second.
• 2016: In April, Samsung announced that they had begun to mass-produce DRAM on a "10 nm-class" process, by which they mean the 1x nm node regime of 16 nm to 19 nm, which supports a 30% faster data transfer rate of 3,200 Mbit/s.^[40] Previously, a size of 20 nm was used.^[41][42]

This section needs to be updated. (January 2014)

DDR4 chips use a 1.2 V supply^{[9]: 16 [46][47]} with a 2.5 V auxiliary supply for wordline boost called V_PP,^[9]: 16 as compared with the standard 1.5 V of DDR3 chips, with lower voltage variants at 1.35 V appearing in 2013. DDR4 is expected to be introduced at transfer rates of 2133 MT/s,^[9]: 18 estimated to rise to a potential 4266 MT/s^[39] by 2013. The minimum transfer rate of 2133 MT/s was said to be due to progress made in DDR3 speeds which, being likely to reach 2133 MT/s, left little commercial benefit to specifying DDR4 below this speed.^[33][39] Techgage interpreted Samsung's January 2011 engineering sample as having CAS latency of 13 clock cycles, described as being comparable to the move from DDR2 to DDR3.^[31]

Internal banks are increased to 16 (4 bank select bits), with up to 8 ranks per DIMM.^[9]: 16

Protocol changes include:^[9]: 20

• Parity on the command/address bus
• Data bus inversion (like GDDR4)
• CRC on the data bus
• Independent programming of individual DRAMs on a DIMM, to allow better control of on-die termination.

Increased memory density is anticipated, possibly using TSV ("through-silicon via") or other 3D stacking processes.^{[33][39][48][49]} The DDR4 specification will include standardized 3D stacking "from the start" according to JEDEC,^[49] with provision for up to 8 stacked dies.^[9]: 12 X-bit Labs predicted that "as a result DDR4 memory chips with very high density will become relatively inexpensive".^[39]

Switched memory banks are also an anticipated option for servers.^[33][48]

In 2008 concerns were raised in the book Wafer Level 3-D ICs Process Technology that non-scaling analog elements such as charge pumps and voltage regulators, and additional circuitry "have allowed significant increases in bandwidth but they consume much more die area". Examples include CRC error-detection, on-die termination, burst hardware, programmable pipelines, low impedance, and increasing need for sense amps (attributed to a decline in bits per bitline due to low voltage). The authors noted that, as a result, the amount of die used for the memory array itself has declined over time from 70–78% for SDRAM and DDR1, to 47% for DDR2, to 38% for DDR3 and to potentially less than 30% for DDR4.^[50]

The specification defined standards for ×4, ×8 and ×16 memory devices with capacities of 2, 4, 8 and 16 Gbit.^[1][51]

In addition to bandwidth and capacity variants, DDR4 modules can optionally implement:

• ECC, which is an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional ECC in their designation. PC4-19200 ECC or PC4-19200E is a PC4-19200 module with ECC.^[52]
• Be "registered" ("buffered"), which improves signal integrity (and hence potentially clock rates and physical slot capacity) by electrically buffering the signals at a cost of an extra clock of increased latency. Those modules are identified by an additional R in their designation, e.g. PC4-19200R. Typically modules with this designation are actually ECC Registered, but the 'E' of 'ECC' is not always shown. Whereas non-registered (a.k.a. unbuffered RAM) may be identified by an additional U in the designation. e.g. PC4-19200U.^[52]
• Be Load reduced modules, which are designated by LR and are similar to registered/buffered memory, in a way that LRDIMM modules buffer both control and data lines while retaining the parallel nature of all signals. As such, LRDIMM memory provides larger overall maximum memory capacities, while addressing some of the performance and power consumption issues of FB memory induced by the required conversion between serial and parallel signal forms.^[52]

At the 2016 Intel Developer Forum, the future of DDR5 SDRAM was discussed. The specifications were finalized at the end of 2016 – but no modules will be available before 2020.^[61] Other memory technologies – namely HBM in version 3 and 4^[62] – aiming to replace DDR4 have also been proposed.

In 2011, JEDEC published the Wide I/O 2 standard; it stacks multiple memory dies, but does that directly on top of the CPU and in the same package. This memory layout provides higher bandwidth and better power performance than DDR4 SDRAM, and allows a wide interface with short signal lengths. It primarily aims to replace various mobile DDRX SDRAM standards used in high-performance embedded and mobile devices, such as smartphones.^[63][64] Hynix proposed similar High Bandwidth Memory (HBM), which was published as JEDEC JESD235. Both Wide I/O 2 and HBM use a very wide parallel memory interface, up to 512 bits wide for Wide I/O 2 (compared to 64 bits for DDR4), running at a lower frequency than DDR4.^[65] Wide I/O 2 is targeted at high-performance compact devices such as smartphones, where it will be integrated into the processor or system on a chip (SoC) packages. HBM is targeted at graphics memory and general computing, while HMC targets high-end servers and enterprise applications.^[65]

Micron Technology's Hybrid Memory Cube (HMC) stacked memory uses a serial interface. Many other computer buses have migrated towards replacing parallel buses with serial buses, for example by the evolution of Serial ATA replacing Parallel ATA, PCI Express replacing PCI, and serial ports replacing parallel ports. In general, serial buses are easier to scale up and have fewer wires/traces, making circuit boards using them easier to design.^[66][67][68]

In the longer term, experts speculate that non-volatile RAM types like PCM (phase-change memory), RRAM (resistive random-access memory), or MRAM (magnetoresistive random-access memory) could replace DDR4 SDRAM and its successors.^[69]

GDDR5 SGRAM is a graphics type of DDR3 synchronous graphics RAM, which was introduced before DDR4, and is not a successor to DDR4.

• Synchronous dynamic random-access memory – main article for DDR memory types
• List of interface bit rates
• Memory timings