In the electronics industry, dark silicon is the amount of circuitry of an integrated circuit that cannot be powered-on at the nominal operating voltage for a given thermal design power (TDP) constraint.

Dennard scaling would posit that as transistors get smaller, they become more efficient in proportion to the increase in number for a given area, but this scaling has broken down in recent years, meaning that increases in the efficiency of smaller transistors are not proportionate with the increase in their number. This discontinuation of scaling has led to sharp increases in power density that hamper powering-on all transistors simultaneously while keeping temperatures in a safe operating range.^[1]

As of 2011, researchers from different groups have projected that, at 8 nm technology nodes, the amount of dark silicon may reach up to 50–80%^[2] depending upon the processor architecture, cooling technology, and application workloads. Dark silicon may be unavoidable even in server workloads with abundance of inherent client request-level parallelism.^[3]

The emergence of dark silicon introduces several challenges for the architecture, electronic design automation (EDA), and hardware-software co-design communities. These include the question of how best to utilize the plethora of transistors (with potentially many dark ones) when designing and managing energy-efficient on-chip many-core processors under peak power and thermal constraints. Architects have initiated several efforts to leverage dark silicon in designing application-specific and accelerator-rich architectures.^[4][5][6]

Recently, researchers have explored how dark silicon exposes new challenges and opportunities for the EDA community.^[7] In particular, they have demonstrated thermal, reliability (soft error and aging), and process variation concerns for dark silicon many-core processors.