In electronic design automation, a floorplan of an integrated circuit is a schematic representation of tentative placement of its major functional blocks.

In modern electronic design process floorplans are created during the floorplanning design stage, an early stage in the hierarchical approach to integrated circuit design.

Depending on the design methodology being followed, the actual definition of a floorplan may differ.

Floorplanning takes in some of the geometrical constraints in a design. Here are some examples:

• bonding pads for off-chip connections (often using wire bonding) are normally located at the circumference of the chip;
• line drivers often have to be located as close to bonding pads as possible;
• chip area is therefore in some cases given a minimum area in order to fit in the required number of pads;
• areas are clustered in order to limit data paths thus frequently featuring defined structures such as cache RAM, multiplier, barrel shifter, line driver and arithmetic logic unit;
• purchased intellectual property blocks (IP-blocks), such as a processor core, come in predefined area blocks;
• some IP-blocks come with legal limitations such as permitting no routing of signals directly above the block.

In some approaches the floorplan may be a partition of the whole chip area into axis aligned rectangles to be occupied by IC blocks. This partition is subject to various constraints and requirements of optimization: block area, aspect ratios, estimated total measure of interconnects, etc.

Finding good floorplans has been a research area in combinatorial optimization. Most of the problems related to finding optimal floorplans are NP-hard, i.e., require vast computational resources. Therefore, the most common approach is to use various optimization heuristics for finding good solutions.

Another approach is to restrict design methodology to certain classes of floorplans, such as sliceable floorplans.

• The Chip Planner of the PLAYOUT System
• VLSI Physical Design: From Graph Partitioning to Timing Closure, by Kahng, Lienig, Markov and Hu, doi:10.1007/978-3-030-96415-3ISBN 978-3-030-96414-6, 2022
• Fundamentals of Layout Design for Electronic Circuits, by Lienig, Scheible, Springer, doi:10.1007/978-3-030-39284-0ISBN 978-3-030-39284-0, 2020