Tile processors^[1] for computer hardware, are multicore or manycore chips that contain one-dimensional, or more commonly, two-dimensional arrays of identical tiles. Each tile comprises a compute unit (or a processing engine or CPU), caches and a switch. Tiles can be viewed as adding a switch to each core, where a core comprises a compute unit and caches.

This article has multiple issues. Please help improve it or discuss these issues on the talk page. (Learn how and when to remove these template messages) A major contributor to this article appears to have a close connection with its subject. (October 2010) This article needs to be updated. (April 2017) This article's factual accuracy may be compromised due to out-of-date information. (April 2017)

In a typical Tile Processor configuration, the switches in each of the tiles are connected to each other using one or more mesh networks.^[2] The Tilera TILEPro64, for example, contains 64 tiles. Each of the tiles comprises a CPU, L1 and L2 caches, and switches for several mesh networks.

Other processors in a tile configuration include SEAforth24, Kilocore KC256, XMOS xCORE microcontrollers, and some massively parallel processor arrays.