Interrupt_vector_table

Interrupt vector table

Interrupt vector table

Data structure

This article is about the general concept. For its implementation found in x86 processors, see Interrupt descriptor table.

An interrupt vector table (IVT) is a data structure that associates a list of interrupt handlers with a list of interrupt requests in a table of interrupt vectors. Each entry of the interrupt vector table, called an interrupt vector, is the address of an interrupt handler (also known as ISR). While the concept is common across processor architectures, IVTs may be implemented in architecture-specific fashions. For example, a dispatch table is one method of implementing an interrupt vector table.

Background

Most processors have an interrupt vector table, including chips from Intel, AMD, Infineon, Microchip[1] Atmel,[2] NXP, ARM[3][4] etc.

Interrupt handlers

Main article: Interrupt handler

Handling methods

An interrupt vector table is used in the three most popular methods of finding the starting address of the interrupt service routine:

"Predefined"

The "predefined" method loads the program counter (PC) directly with the address of some entry inside the interrupt vector table. The jump table itself contains executable code. While in principle an extremely short interrupt handler could be stored entirely inside the interrupt vector table, in practice the code at each entry is a single jump instruction that jumps to the full interrupt service routine (ISR) for that interrupt. The Intel 8080,[5] Atmel AVR[6][7] and all 8051 and Microchip microcontrollers[8] use the predefined approach.

"Fetch"

The "fetch" method loads the PC indirectly, using the address of some entry inside the interrupt vector table to pull an address out of that table, and then loading the PC with that address.[8] Each and every entry of the IVT is the address of an interrupt service routine. All Motorola/Freescale microcontrollers use the fetch method.[8]

"Interrupt acknowledge"

For the "interrupt acknowledge" method, the external device gives the CPU an interrupt handler number. The interrupt acknowledge method is used by the Intel Pentium and many older microprocessors.[8]

When the CPU is affected by an interrupt, it looks up the interrupt handler in the interrupt vector table, and transfers control to it.

See also

References

  1. [1]
    "dsPIC33F Family Reference Manual" section 29.1.1 Interrupt Vector Table
  2. [2]
    "AVR Libc User Manual" section: Introduction to avr-libc's interrupt handling
  3. [3]
    "Documentation – Arm Developer". developer.arm.com. Retrieved 2020-07-26.
  4. [4]
    "Documentation – Arm Developer – AArch64 exception vector table". developer.arm.com. Retrieved 2020-07-26.
  5. [5]
    Intel 8080 Microcomputer Systems User's Manual. Intel Corporation. September 1975. pp. 2–11 Interrupt Sequences. OCLC 2058546. OL 24210843M.
  6. [6]
    Roger L. Traylor. "Interrupts: AVR interrupt servicing"
  7. [7]
    Gary Hill. "Atmel AVR Interrupt and Timing Subsystems: ATMEGA328P interrupt vector table"
  8. [8]
    Huang, Han-Wat (2005). Pic Microcontroller: An Introduction to Software and Hardware Interfacing. Cengage Learning. p. 247. ISBN 978-1-4018-3967-3. Retrieved 22 April 2013.
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