Audio Channel Frequency

The AUDF* registers control the frequency or pitch of the corresponding sound channels. The AUDF* values also control the POKEY hardware timers useful for code that must run in precise intervals more frequent than the vertical blank.

Each AUDF* register is an 8-bit value providing a countdown timer or divisor for the pulses from the POKEY clock. So, smaller values permit more frequent output of pulses from POKEY, and larger values, less frequent. The values $0_hex/0_dec to $FF_hex/255_dec are incremented by POKEY to range from $1_hex/1_dec to $100_hex/256_dec. The actual audible sound pitch is dependent on the POKEY clock frequency and distortion values chosen. See Audio Channel Control and Audio Control.

Audio Channel Control

The Audio Channel control registers provide volume and distortion control over individual sound channels. Audio may also be generated independently of the POKEY clock by direct volume manipulation of a sound channel which is useful for playing back digital samples.

AUDCTL $D208 Write

Audio Control allows the choice of clock input used for the audio channels, control over the high-pass filter feature, merging two channels together allowing 16-bit frequency accuracy, selecting a high frequency clock for specific channels, and control over the "randomness" of the polynomial input.

"1" means "on", if not described:

Bit 0

$01: (15 kHz), choice of frequency divider rate "0" - 64 kHz, "1" - 15 kHz

Bit 1

$02: (FI2 + 4), high-pass filter for channel 2 rated by frequency of channel 4

Bit 2

$04: (FI1 + 3), high-pass filter for channel 1 rated by frequency of channel 3

Bit 3

$08: (CH4 + 3), connection of dividers 4+3 to obtain 16-bit accuracy

Bit 4

$10: (CH2 + 1), connection of dividers 2+1 to obtain 16-bit accuracy

Bit 5

$20: (CH3 1.79), set channel 3 frequency "0" is 64 kHz. "1" is 1.79 MHz NTSC or 1.77 MHz PAL

Bit 6

$40: (CH1 1.79), set channel 1 frequency "0" is 64 kHz. "1" is 1.79 MHz NTSC or 1.77 MHz PAL

Bit 7

$80: (POLY 9), switch shift register "0" - 17-bit, "1" – 9-bit

All frequency dividers (AUDF) can be driven at the same time by 64 kHz or 15 kHz rate.

Frequency dividers 1 and 3 can be alternately driven by CPU clock (1.79 MHz NTSC, 1.77 MHz PAL). Frequency dividers 2 and 4 can be alternately driven by output of dividers 1 and 3. In this way, POKEY makes possible connecting of 8-bit channels to create sound with 16-bit accuracy.

Possible channel configurations:

• four 8-bit channels
• two 8-bit channels and one 16-bit channel
• two 16-bit channels

POT0 $D200 Read

SHADOW: PADDL0 $0270

Paddle Controller 0 Input

POT1 $D201 Read

SHADOW: PADDL1 $0271

Paddle Controller 1 Input

POT2 $D202 Read

SHADOW: PADDL2 $0272

Paddle Controller 2 Input

POT3 $D203 Read

SHADOW: PADDL3 $0273

Paddle Controller 3 Input

POT4 $D204 Read

SHADOW: PADDL4 $02704

Paddle Controller 4 Input

POT5 $D205 Read

SHADOW: PADDL5 $0275

Paddle Controller 5 Input

POT6 $D206 Read

SHADOW: PADDL6 $0276

Paddle Controller 6 Input

POT7 $D207 Read

SHADOW: PADDL7 $0277

Paddle Controller 7 Input

Each input has 8-bit timer, counting time when each TV line is being displayed. This had the added advantage of allowing the value read out to be fed directly into screen coordinates of objects being driven by the paddles. The Atari Paddle values range from 0 to 228, though the maximum possible is 244. The Paddle controller reads 0 when turned to its maximum clockwise position, and returns increasing values as it is turned counter-clockwise ending at its maximum value.

The Paddle reading process begins by writing to POTGO which resets the POT* values to 0, the ALLPOT value to $FF, and discharges the potentiometer read capacitors. The POT* values increment as they are being scanned until reaching the resistance value of the potentiometer. When the Paddle reading is complete the corresponding bit in ALLPOT is reset to 0.

The Paddle scanning process can take the majority of a video frame to complete. The Atari Operating System takes care of Paddle reading automatically. The Paddles are read and paddle scanning initiated during the stage 2 vertical blank. Paddle values are copied to shadow registers. (Note that Paddle triggers are actually joystick direction input read from PIA.)

A faster mode of scanning the Paddles is possible by setting a bit in SKCTL. The reading sequence completes in only a couple scan lines, but the value is less accurate.

ALLPOT $D208 Read

Potentiometer Scanning Status

Each bit corresponds to one potentiometer input (the POT* registers). When paddle scanning is started by writing to POTGO each paddle's bit in ALLPOT is set to 1. When a paddle's scan is complete the corresponding bit in ALLPOT is reset to 0 indicating the value in the associated POT* register is now valid to read.

POTGO $D20B Write

Start Potentiometer Scan

Writing to POTGO initiates the potentiometer (Paddle) scanning process. This resets the POT* values to 0, the ALLPOT value to $FF, and discharges the potentiometer read capacitors. As each potentiometer scan completes the bit corresponding to the potentiometer in ALLPOT is cleared indicating the value of the associated POT* register is valid for reading.

SKREST $D20A Write

Reset Serial Port Status (SKSTAT).

A write to this register will reset bits 5 through 7 of SKSTAT which are latches to 1. The latches flag keyboard overrun, Serial data input overrun, and Serial data input frame error.

SEROUT $D20D Write

Serial port data output byte.

This is a parallel "holding" register for the eight bit (one byte) value that will be transferred to the serial shift register for output one bit at a time. When the port is ready to accept data for output a Serial Data Out interrupt informs the Operating System that it can write a byte to this output register.

SERIN $D20D Read

Serial port data input byte.

Like SEROUT, also a parallel "holding" register. This holds the eight bit (one byte) value assembled by the serial shift register reading the data input one bit at a time. When a full byte is read a Serial Data In interrupt occurs informing the Operating System that it can read the byte from this register.

SKCTL $D20F Write

Serial Port Control

Bit 0: Enable "debounce" scanning which is intended to eliminate noise or jitter from mechanical switches. A value of 1 enables POKEY to use an internal comparison register while scanning keys. A key must be detected in two simultaneous scans before it is identified as pressed, and it must be seen released for two consecutive scans to be considered released. This should be enabled to maintain normal keyboard handling with the Operating System.

Bit 1: Set to 1 to enable keyboard scanning. This should be enabled to maintain normal keyboard handling with the Operating System.

Bit 2: Set to 1 to enable fast, though less accurate Potentiometer scanning. Fast Pot scanning increments the counter on every cycle and returns a usable result within two scan lines. The Operating System uses the slow Pot Scanning which increments the counter once every 114 cycles (scan line) taking a frame (1/60th second) to produce a result. The OS reads the Pot values during its Vertical Blank Interrupt (VBI) and copies the result to the potentiometer Shadow registers in RAM. It then resets POTGO for the next read during the next VBI.

Bit 3: Enable Serial port two-tone mode. When enabled, 1 and 0 bits output to the SIO bus are replaced by tones set by timers 1 and 2. This is ordinarily used for writing analog tones representing digital data to cassette tape.

Bit 4-6: Clock Timing Control for serial port operation. Bit values described below:

Bit 7: Forces a known 0 output, so that timer 2 can reset timer 1 in two-tone serial output mode.

SKSTAT $D20F Read

Serial Port Status

KBCODE $D209 Read

SHADOW: CH $02FC

Keyboard Code