Template:AMD_Radeon_Instinct

Template:AMD Radeon Instinct

More information Model (Code name), Launch ...

Model (Code name)	Launch	Architecture & fab	Transistors & die size	Core		Fillrate^{[lower-alpha 1]}^{[lower-alpha 2]}^{[lower-alpha 3]}		Processing power^{[lower-alpha 1]}^{[lower-alpha 4]} (TFLOPS)			Memory				TBP	Bus interface
Model (Code name)	Launch	Architecture & fab	Transistors & die size	Config^{[lower-alpha 5]}	Clock^{[lower-alpha 1]} (MHz)	Texture (GT/s)	Pixel (GP/s)	Half	Single	Double	Size (GB)	Bus type & width	Bandwidth (GB/s)	Clock (MT/s)	TBP	Bus interface
Radeon Instinct MI6 (Polaris 10)^[1]^[2]^[3]^[4]^[5]^[6]	Jun 20, 2017	GCN 4 GloFo 14LP	5.7×10⁹ 232 mm²	2304:144:32 36 CU	1120 1233	161.3 177.6	35.84 39.46	5.161 5.682	5.161 5.682	0.323 0.355	16	GDDR5 256-bit	224	7000	150 W	PCIe 3.0 ×16
Radeon Instinct MI8 (Fiji)^[1]^[2]^[3]^[7]^[8]^[9]		GCN 3 TSMC 28 nm	8.9×10⁹ 596 mm²	4096:256:64 64 CU	1000	256.0	64.00	8.192	8.192	0.512	4	HBM 4096-bit	512	1000	175 W
Radeon Instinct MI25 (Vega 10)^[1]^[2]^[3]^[10]^[11]^[12]^[13]		GCN 5 GloFo 14LP	12.5×10⁹ 510 mm²	4096:256:64 64 CU	1400 1500	358.4 384.0	89.60 96.00	22.94 24.58	11.47 12.29	0.717 0.768	16	HBM2 2048-bit	484	1890	300 W
Radeon Instinct MI50 (Vega 20)^[14]^[15]^[16]^[17]^[18]^[19]	Nov 18, 2018	GCN 5 TSMC N7	13.2×10⁹ 331 mm²	3840:240:64 60 CU	1450 1725	348.0 414.0	92.80 110.4	22.27 26.50	11.14 13.25	5.568 6.624	16 32	HBM2 4096-bit	1024	2000		PCIe 4.0 ×16
Radeon Instinct MI60 (Vega 20)^[15]^[20]^[21]^[22]	Nov 18, 2018	GCN 5 TSMC N7	13.2×10⁹ 331 mm²	4096:256:64 64 CU	1500 1800	384.0 460.8	96.00 115.2	24.58 29.49	12.29 14.75	6.144 7.373	32		1024	2000
AMD Instinct MI100 (Arcturus)^[23]^[24]^[25]	Nov 16, 2020	CDNA TSMC N7	25.6×10⁹ 750 mm²	7680:480:- 120 CU	1000 1502	480.0 721.0	—	122.9 184.6	15.36 23.07	7.680 11.54	32		1228.8	2400
AMD Instinct MI210 (Aldebaran)^[26]^[27]^[28]	Mar 22, 2022	CDNA 2 TSMC N6	28 x 10⁹ ~770 mm²	6656:416:- 104 CU (1 × GCD)^{[lower-alpha 6]}	1000 1700	416.0 707.2		106.5 181.0	13.31 22.63	13.31 22.63	64	HBM2E 4096-bit	1638.4	3200
AMD Instinct MI250 (Aldebaran)^[29]^[30]^[31]	Nov 8, 2021		58 x 10⁹ 1540 mm²	13312:832:- 208 CU (2 × GCD)		832.0 1414		213.0 362.1	26.62 45.26	26.62 45.26	2 × 64	HBM2E 2 × 4096-bit^{[lower-alpha 7]}	2 × 1638.4		500 W 560 W (Peak)
AMD Instinct MI250X (Aldebaran)^[32]^[30]^[33]	Nov 8, 2021		58 x 10⁹ 1540 mm²	14080:880:- 220 CU (2 × GCD)		880.0 1496		225.3 383.0	28.16 47.87	28.16 47.87	2 × 64	HBM2E 2 × 4096-bit^{[lower-alpha 7]}	2 × 1638.4		500 W 560 W (Peak)
AMD Instinct MI300A (Antares)^[34]^[35]^[36]^[37]	Dec 6, 2023	CDNA 3 TSMC N5 & N6	146 x 10⁹ 1017 mm²	14592:912:- 228 CU (6 × XCD) (24 AMD Zen 4 x86 CPU cores)	2100	912.0 1550.4		980.6 1961.2 (With Sparsity)	122.6	61.3 122.6 (FP64 Matrix)	128	HBM3 8192-bit	5300	5200	550 W 760 W (Liquid Cooling)	PCIe 5.0 ×16
AMD Instinct MI300X (Aqua Vanjaram)^[38]^[39]^[40]^[41]	Dec 6, 2023	CDNA 3 TSMC N5 & N6	153 x 10⁹ 1017 mm²	19456:1216:- 304 CU (8 × XCD)	2100	1216.0 2062.1		1307.4 2614.9 (With Sparsity)	163.4	81.7 163.4 (FP64 Matrix)	192	HBM3 8192-bit	5300	5200	750 W	PCIe 5.0 ×16

Boost values (if available) are stated below the base value in italic.
Texture fillrate is calculated as the number of texture mapping units multiplied by the base (or boost) core clock speed.
Pixel fillrate is calculated as the number of render output units multiplied by the base (or boost) core clock speed.
Precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
Unified shaders : Texture mapping units : Render output units and Compute units (CU)
GCD Refers to a Graphics Compute Die. Each GCD is a different piece of silicon.
CDNA 2.0 Based cards adopt a design using two dies on the same package.They are linked with 400GB/s Bidirectional Infinity Fabric link, The dies are addressed as individual GPUs by the host system.

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This article uses material from the Wikipedia article Template:AMD_Radeon_Instinct, and is written by contributors. Text is available under a CC BY-SA 4.0 International License; additional terms may apply. Images, videos and audio are available under their respective licenses.

[boost-1] Boost values (if available) are stated below the base value in italic.

[texture_fill-2] Texture fillrate is calculated as the number of texture mapping units multiplied by the base (or boost) core clock speed.

[pixel_fill-3] Pixel fillrate is calculated as the number of render output units multiplied by the base (or boost) core clock speed.

[FLOPS-4] Precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

[cconfig-5] Unified shaders : Texture mapping units : Render output units and Compute units (CU)

[GCD_cdna2-34] GCD Refers to a Graphics Compute Die. Each GCD is a different piece of silicon.

[mgpu_cdna2-38] CDNA 2.0 Based cards adopt a design using two dies on the same package.They are linked with 400GB/s Bidirectional Infinity Fabric link, The dies are addressed as individual GPUs by the host system.

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